1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a method for manufacturing a thin-film transistor (TFT) substrate.
2. The Related Arts
With the progress of the display technology, flat panel display devices, such as liquid crystal displays (LCDs), due to various advantages, such as high image quality, low power consumption, thin device body, and wide range of applications, have been widely used in all sorts of consumer electronic products, including mobile phones, televisions, personal digital assistants (PDAs), digital cameras, notebook computers, and desktop computers, making them the main stream of display devices.
Most of the liquid crystal display devices that are currently available in the market are backlighting LCDs, which comprise a liquid crystal display panel and a backlight module. The working principle of the liquid crystal display panel is that liquid crystal molecules are disposed between two parallel glass substrates and multiple vertical and horizontal tiny conductive wires are arranged between the two glass substrates, wherein the liquid crystal molecules are controlled to change directions through application of electricity in order to refract out light emitting from the backlight module to generate an image.
The liquid crystal display panel is generally made up of a color filter (CF) substrate, a thin-film transistor (TFT) substrate, liquid crystal (LC) interposed between the CF substrate and the TFT substrate, and sealant and is generally manufactured with a process involving an anterior stage of array engineering (for thin film, photolithography, etching, and film peeling), an intermediate stage of cell engineering (for lamination of the TFT substrate and the CF substrate), and a posterior stage of module assembly (for combining a drive integrated circuit (IC) and a printed circuit board). Among these stages, the anterior stage of array engineering generally involves the formation the TFT substrate for controlling the movement of liquid crystal molecules; the intermediate stage of cell engineering generally involves filling liquid crystal between the TFT substrate and the CF substrate; and the posterior stage of module assembly generally involves the combination of the drive IC and the printed circuit board for driving the liquid crystal molecules to rotate for displaying of images.
An amorphous In—Ga—Zn—O (a-IGZO) thin-film transistor (TFT) has various advantages, including high electron mobility, low leakage current, and low manufacturing temperature, has attracted wide attention. A conventional bottom gate structure based oxide semiconductor transistor, due to a relatively large overlapping area between a gate electrode and a source electrode thereof, may generate relatively large parasitic capacitance, which leads to delay of signals, and, in addition, a transistor so manufactured shows a relatively large size, imposing constraints to the applications thereof. A top gate self-alignment structure has no overlapping between the source/drain electrode and the gate electrode and thus shows reduced parasitic capacitance and bettered malleability.
As shown in FIGS. 1-7, a convention process for manufacturing a top-gate self-alignment oxide thin-film transistor substrate is shown, comprising the following steps:
Step 1: as shown in FIG. 1, providing a base plate 100 and depositing a buffer layer 200 on the base plate 100;
Step 2: as shown in FIGS. 2-3, depositing a semiconductor layer 300 on the buffer layer 200 and using one mask to subject the semiconductor layer 300 to patterning treatment so as to form an active layer 350;
Step 3: as shown in FIG. 4, depositing, in sequence, an insulation layer 400 and a gate metal layer 500 on the active layer 350 and the buffer layer 200, coating a layer of photoresist material on the gate metal layer 500, and using one mask to subject the layer of photoresist material to patterning treatment so as to form a photoresist layer 600 corresponding to a middle portion of the active layer 350;
Step 4: as shown in FIG. 5, subjecting the gate metal layer 500 and the insulation layer 400 to etching with the photoresist layer 600 as a blocking layer so as to form a gate electrode 550 and a gate insulation layer 450; and subjecting the active layer 350 to treatment, with the photoresist layer 600, the gate electrode 550, and the gate insulation layer 450 as a blocking layer, so as to form a source contact zone 310, a drain contact zone 320, and a channel zone 330 located between the source contact zone 310 and the drain contact zone 320;
Step 5: as shown in FIG. 6, depositing an interlayer dielectric layer 700 on the gate electrode 550, the active layer 350, and the buffer layer 200, and using one mask to subject the interlayer dielectric layer 700 to patterning treatment so as to form, in the interlayer dielectric layer 700, a first via 710 and a second via 720 respectively corresponding to the source contact zone 310 and the drain contact zone 320;
Step 6: as shown in FIG. 7, depositing a source/drain metal layer on the interlayer dielectric layer 700, and using one mask to subject the source/drain metal layer to patterning treatment so as to forma source electrode 810 and a drain electrode 820, wherein the source electrode 810 and the drain electrode 820 are respectively in contact engagement with the source contact zone 310 and the drain contact zone 320 of the active layer 350 through the first via 710 and the second via 720 thereby forming a top-gate self-alignment oxide thin-film transistor substrate.
In the above-described process for manufacturing a top-gate self-alignment oxide thin-film transistor substrate, four masks are needed so that the manufacturing time is extended, the process is complicated, and the manufacturing cost is high.